1. Field of the Invention
This invention relates generally to data processing systems, and more particularly, to data processing systems having a central processing unit generally adapted for pipelined execution of instructions. The central processing unit contemplated herein includes a coprocessor unit for performing operations, such as floating point operations, that require an interval time which is longer than the unit of time for which the remainder of the (pipelined) central processing unit has been designed. The operations performed by the coprocessor unit must be synchronized with the remainder of the central processing unit.
2. Description of the Related Art
In order to increase the speed of execution of instructions by a central processing unit, the technique of pipelining the instruction execution has been adapted. In this technique, as illustrated in the example of FIG. 1A and FIG. 1B, the execution of an instruction I, typically requiring a time T for execution, is divided into a plurality of operations, A, B, C, and D. The central processor is partitioned in such a manner that each operation of the instruction is completed in a predefined time period T.sub.0. The result of this partitioning (generally referred to as a four stage pipeline in the present example) is that, as illustrated in FIG. 1A, the instruction that required a time T for execution, now requires a time 4T.sub.0 for instruction execution. Because of the added apparatus required for the partitioning of the central processing unit, the time T for execution of an instruction is typically longer than the execution of the instruction in a non-pipelined central processing unit. Because the time period T.sub.0 for each operation is shorter than the length of time T for the execution of the instruction 1, and as a result of the partitioning of the central processing unit for apparatus separately executing each operation of the instruction, an instruction can be initiated in the central processing unit after a time period T.sub.0 rather than after a time period T as in the non-pipelined mode of operation. Similarly, an instruction can be completed after each T.sub.0 time period in the pipelined mode of operation. Therefore, execution of instruction sequence in the pipelined mode of operation can be expedited even though the execution of each individual instruction requires a longer period of time. As will be clear, the interval T.sub.0 is chosen as small as possible consistent with the number of stages in the pipelined execution unit and the most time consuming operation in the partitioned group of instructions.
In the central processing unit, several types of special instructions require more complex processing than is required in the normal processing of logic signal groups through the central processing unit pipeline. A first instruction type involves quantities that are represented by two of the standard logic signal groups, generally referred to as double precision logic signal groups. The use of double precision logic signal groups permits greater accuracy in the representation of a number. A second type of instruction that requires more complex processing involves the floating point representations of numbers. In the floating point representation, a number is represented by a fraction logic signal group and by an exponent argument logic signal group. The exponent argument logic signal group represents the power to which the base exponent is raised while the fraction logic signal group represents a multiplier of the exponential quantity. The floating point number is normalized when not being processed, normalization meaning that a logic "1" signal is entered in the most significant fraction logic signal group position and the exponent argument logic signal group is adjusted accordingly. A third type of instruction that requires special processing includes integer multiplication and integer division. Both the integer multiplication and the integer division instructions require multiple steps and cannot be accommodated within a single timing cycle available for operation in a pipelined central processing unit of a data processing system. In these examples of special types of instructions requiring complex processing of the associated signal groups, the result is that the operation implementing actual data signal group manipulation will require a longer time period than the predefined period of time allotted for each instruction operation by the pipelined central processing unit. By way of example, the addition or subtraction of floating point quantities requires a comparison of the exponent argument quantities and, in the case where equality is not present, an adjustment of the exponent argument logic signal group along with the associated fraction logic signal group before the actual subtraction of the fractions can be performed. Thus, the processing of floating point quantities and double precision quantities cannot be performed in the predefined operation time (T.sub.0) of the other stages of the central processing unit.
In order to accommodate the relatively slow execution of these special instructions, the interval for execution of the operations of the pipelined instruction can be chosen to accommodate this relatively lengthy interval required for operation execution. As an example, a double precision floating point division operation can occupy 58 time intervals of an associated pipelined central processing unit in the preferred embodiment. This technique for the accommodation of the relatively slow operation execution speed of the special instructions by lengthening the predefined interval available at each central processing unit pipeline stage provides an unacceptably large negative impact on the execution speed of the instruction sequence.
Similarly, the central processing unit can be adapted to halt operation in response to the presence of an operation execution by the special instructions. This interruption can also impact the speed of execution of an instruction sequence, particularly when a substantial portion of the instructions involve the special operations.
Because the special instructions cannot be accommodated in the main data processing sequence apparatus, the operations on the data signal groups specified by the instructions are performed in central processing unit subsystem, generally referred to as the coprocessor unit, operating in parallel with the main instruction sequence apparatus. The operation of the coprocessor unit is subject to the restriction that the operation must be compatible with the operation of the remainder of the central processing unit.
A need has therefore been felt for apparatus and method for accommodation of relatively long time interval required for the execution of special instructions by a coprocessor unit while retaining the advantages of the pipelined mode of operation.